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XDBus: a high-performance, consistent, packet-switched VLSI bus

By: Frailong, J.-M.; Sindhu, P.; Curry, D.; Gunning, B.; Yuan, L.; Cekleov, M.; Gastinel, J.;

1993 / IEEE / 0-8186-3400-6

Description

This item was taken from the IEEE Periodical ' XDBus: a high-performance, consistent, packet-switched VLSI bus ' The XDBus is a low-cost, synchronous, packet-switched VLSI bus designed for use in high-performance multiprocessors. The bus provides an efficient coherency protocol which guarantees processors a consistent view of memory in the presence of caches and IO. Low-voltage swing (GTL) CMOS drivers connected to balanced transmission line traces ensure low power as well as high speed for chip, board, and as backplane applications. The signaling scheme and coherency protocol work together to promote a high level of system integration, while permitting a wide variety of configurations to be realized. These configurations include small single board systems, multiple bus systems, multiboard backplane systems, and multilevel cache systems. The bus is used in several commercial systems including Sun Microsystem's new SPARCcenter 2000 series.<>