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An architecture for rate-distortion optimized motion estimation

By: Kalapatapu, V.; Srinivas, P.V.; Varadarajan, S.; Bayoumi, M.A.;

1993 / IEEE / 0-7803-1760-2

Description

This item was taken from the IEEE Periodical ' An architecture for rate-distortion optimized motion estimation ' In this paper, we propose an architecture for motion estimation using variable block matching scheme. It is based on recent advances in rate allocation theory, developed for computing rate-distortion optimized movement compensation. The optimum motion vector and the best quad tree decomposition are determined in a closed loop optimization procedure. Only the quadtree and the motion vector, which are considered to provide the absolute minimum update information, are coded and transmitted. The proposed tree architecture supports pipelined operations. The architecture is suitable for VLSI implementation, owing to modular properties. The Processing Elements (PEs) also support pipelining. An Application Specific circuit prototype has been designed for 4/spl times/4 image blocks. The proposed architecture is scalable and can be easily be adopted for large image blocks.<>