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A BiCMOS 50 MHz cache controller for a superscalar microprocessor

By: Tucker, C.; Wang, C.; Rogers, A.; Reed, J.; Reaves, J.; Rusu, S.; Nguyen, S.; Nettleton, N.; Krishnamurthi, A.; Cruz-Rios, J.; Berg, C.; Anand, R.K.; Joshi, B.; Chang, J.-H.; Yee, D.; Wong, M.;

1992 / IEEE / 0-7803-0573-6

Description

This item was taken from the IEEE Periodical ' A BiCMOS 50 MHz cache controller for a superscalar microprocessor ' A description is given of a BiCMOS 50-MHz, 2.2 M-transistor cache controller (CC) chip which supports up to 2 MB of direct-mapped secondary cache for a superscalar microprocessor chip (PU) and interfaces with two multiprocessor (MP) buses. One is the MBus, a circuit-switched MP system bus operating at TTL (transistor-transistor logic) levels. The other is the XBus, a local packet-switched bus operating at either TTL or Gunning-transceiver logic (GTL) levels. In XBus mode, the CC connects to MP buses through buswatcher chips, up to four of which can be connected to the CC to support 4 MP buses. With XBus interface, the CC can support customized MP buses.<>