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A second-level cache controller for a super-scalar SPARC processor

By: Nettleton, N.; Krishnamurthy, A.; Joshi, B.; Cruz-Rios, J.; Berg, C.; Nguyen, S.; Chang, J.-H.; Wong, M.; Anand, R.K.; Wang, C.; Tucker, C.;

1992 / IEEE / 0-8186-2655-0

Description

This item was taken from the IEEE Periodical ' A second-level cache controller for a super-scalar SPARC processor ' The design of a BiCMOS 50-MHz, 2.2-million transistor, second-level cache controller chip (CC) for a SPARC super-scalar CPU (PU) is described. This chip is designed to control up to 2 MB of second-level cache (E$) so that the effective memory latency is reduced, and to support two different multiprocessor (MP) system buses, the MBus and the Dynabus. CC isolates PU and E$, which operate with a faster processor clock, from the rest of the system, which may operate with a slower system clock, through multiple FIFOs (first in, first out's) and synchronizers. With the isolation, the PU can access E$ in a pipelined fashion with a peak rate of one double-word (64-bit/DW) every processor cycle for both read and write.<>