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A 1.28 mu m/sup 2/ contactless memory cell technology for a 3 V-only 64 Mbit EEPROM

By: Miyamoto, N.; Okazaki, T.; Sasaki, T.; Kato, M.; Tanaka, T.; Adachi, T.; Saeki, S.; Kume, H.; Nishida, T.; Morimoto, T.; Yugami, J.; Ushiyama, M.; Ohji, Y.;

1992 / IEEE / 0-7803-0817-4

Description

This item was taken from the IEEE Periodical ' A 1.28 mu m/sup 2/ contactless memory cell technology for a 3 V-only 64 Mbit EEPROM ' This paper describes a novel contactless memory cell technology for a 3V-only 64Mbit EEPROM with NOR structure. A new program/erase scheme using a Fowler-Nordheim tunneling mechanism is developed, resulting in a single 3V power supply operation. Scatter in ""low-level"" threshold voltage in a memory array, which seriously affects a read operation margin at a reduced V/sub c/c in the NOR structure, is also improved with this scheme. Based on a 0.4 mu m CMOS process, a small cell area of 1.28 mu m/sup 2/ is successfully realized by the contactless memory cell technology, demonstrating the 64Mbit integration capability.<>