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Pipelined concurrent simulation on distributed-memory parallel computers

By: Tai, S.-E.; Bhattacharya, D.;

1991 / IEEE / 0-8186-2125-7

Description

This item was taken from the IEEE Periodical ' Pipelined concurrent simulation on distributed-memory parallel computers ' Presents a space- and time-efficient approach to fault simulation on distributed-memory message-passing parallel computers. The processors in the parallel machine, and the host, communicate in a pipelined fashion where each processor simulates only one partition of the circuit under consideration using the concurrent simulation approach. If good load balancing can be obtained, this approach leads to nearly linear speedup when a large number of vectors are simulated. Further, practical implementations of this approach uses memory in the parallel machine efficiently. A preliminary implementation of this approach on an Intel hypercube machine is then described. Experimental results obtained using the ISCAS85 benchmark circuits confirm the prediction that the actual speedup is primarily dependent on the load distribution across processors. Further, simple circuit partitioning heuristic is seen to provide moderate to good speedup in most cases.<>