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A multi-chip packaged GaAs 16*16 bit parallel multiplier

By: Hayashi, H.; Shiga, N.; Nishiguchi, M.; Hirose, T.; Sawada, S.; Sekiguchi, T.;

1990 / IEEE

Description

This item was taken from the IEEE Periodical ' A multi-chip packaged GaAs 16*16 bit parallel multiplier ' A GaAs 16*16 16-bit parallel multiplier utilizing multichip packaging technology is demonstrated. This multichip approach was taken in an effort to realize GaAs ULSIs with high yield and reliability, using multiple smaller scale integrated circuits. The device is composed of four GaAs 8*8-bit expandable parallel multipliers and a multichip package (MCP). The developed 8*8 multipliers consist of 1097 enhancement/depletion DCFL (directly coupled FET logic) gates each, and have a 3.4 ns multiplication time. The developed MCP is composed of five layers of alumina ceramic which include 50 Omega striplines. The multiplication time of this 16*16-bit multichip multiplier is 7.6 ns, and the total production yield is 70%.<>