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An 80 ns 1 Mb flash memory with on-chip erase/erase-verify controller

By: Adachi, T.; Tanaka, T.; Shimohigashi, K.; Wada, T.; Komori, K.; Nishimoto, T.; Izawa, K.; Hagiwara, T.; Kubota, Y.; Shohji, K.; Miyamoto, N.; Saeki, S.; Ogawa, N.; Ushiyama, M.; Ohji, Y.; Kume, H.; Seki, K.;

1990 / IEEE


This item was taken from the IEEE Periodical ' An 80 ns 1 Mb flash memory with on-chip erase/erase-verify controller ' An internal erase and erase-verify control system implemented in all electrically erasable, reprogrammable, 80-ns, 1-Mb flash memory suitable for in-system reprogram applications is discussed. This system features a command signal latch, a sequence controller, and a verify voltage generator. Timing in the electrical erase mode is shown. The erase mode is initiated by a 50-ns pulse. An erase and erase-verify sequence is automatically conducted in a chip without any further external control. The internal status can be checked through a status-polling mode. The 80-ns access time results from advanced sense amplifiers, as well as from low-resistance polysilicide word lines and scaled periphery transistors. For sensitivity and speed of the sense circuits, a pMOSFET with gate connected to drain is used as a load transistor. Compared with a conventional sense amplifier with a grounded-gate pMOSFET load, the shorter channel length of the pMOSFET used here gives the same sensitivity, reducing the stray capacitance problem. Together with a signal voltage swing reduced by a threshold voltage of the pMOSFET, this is essential for access speed. Simulation shows a 30-ns reduction of access time at a V/sub cc/ of 4.25 V. Schmoo plots of the address access time indicate that V/sub cc min/ is 3.4 V, demonstrating the proper operation of the automatic erase scheme.<>