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4 Gb/s GaAs gate arrays with 0.5 mu m WSi-gate MESFET technology

By: Tanaka, Y.; Kanamori, M.; Setoyama, Y.; Tsuchiya, T.; Hosono, Y.; Uetake, K.; Saito, H.; Hirayama, H.; Kishi, K.; Furutsuka, T.;

1989 / IEEE

Description

This item was taken from the IEEE Periodical ' 4 Gb/s GaAs gate arrays with 0.5 mu m WSi-gate MESFET technology ' GaAs 200-gate and 500-gate arrays operating at up to 4 Gb/s have been successfully developed using 0.5- mu m WSi-gate MESFET technology. The arrays had emitter coupled logic (ECL)-compatible interfaces and -2/-3.5-V or -2/-4.5-V power supply voltage and were composed of mask-programmable four-input NOR gates, implemented with a one-diode BFL circuit. The unloaded delay times were 35 ps/gate for the 200-gate arrays and 44 ps/gate for the 500-gate arrays. The maximum operating speeds of the test circuits were 4.6 Gb/s for a 4 bit 2-to-1 multiplexer (MUX), more than 5 Gb/s for a 4-bit 1-to-2 demultiplexer (DEMUX), and 3.6 Gb/s for a 4-to-1 MUX. ECL level compatibilities were successfully obtained at up to 4 Gb/s.<>