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A 9 ns 1 Mb CMOS SRAM
By: Nishida, T.; Hashimoto, N.; Ishibashi, K.; Yamanaka, T.; Shimohigashi, K.; Hanamura, S.; Sasaki, K.; Honjo, S.;
1989 / IEEE
This item was taken from the IEEE Periodical ' A 9 ns 1 Mb CMOS SRAM ' A 1-Mb (256k*4/1M*1) CMOS SRAM (static random access memory), fabricated using a half-micron triple-poly double-metal CMOS technology, is reported. A 9-ns access time is attained with 5-V supply and 30-pF load capacitance. This access time has been achieved with a three-stage pMOS cross-coupled sense amplifier, 0.6- mu m high-performance MOSFETs, and an optimized internal supply voltage scheme. A redundancy scheme with no access time penalty has been incorporated. The sense amplifier circuit combined with a CMOS cross-coupled preamplifier has under 10-ns access time. Address and data output waveforms are shown. Typical active current is 55 mA at 30 MHz, and typical standby current is 15 mA (TTL). Typical RAM characteristics are listed.<
Three-stage Pmos Cross-coupled Sense Amplifier
Optimized Internal Supply Voltage Scheme
Data Output Waveforms
Random Access Memory
Triple-poly Double-metal Cmos Technology
Static Random Access Memory
Address Output Waveform
Integrated Memory Circuits
Cmos Integrated Circuits