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A 3.5 ns, 500 mW 16 kb BiCMOS ECL RAM
By: Watanabe, A.; Tachibana, S.; Suzuki, M.; Shimohigashi, K.; Nagano, T.; Higuchi, H.; Shukuri, S.;
1989 / IEEE
This item was taken from the IEEE Periodical ' A 3.5 ns, 500 mW 16 kb BiCMOS ECL RAM ' A 16-Kb RAM was designed and fabricated using a 0.5- mu m BiCMOS technology. It has a typical address access time of 3.5 ns. The RAM operates at a supply voltage of -4.5 V and features 500-mW power dissipation. A description is given of two techniques crucial to high-speed, low-power design: a wired -OR precoder combined with a low-power, high-speed level converter circuit and a direct column-sensing circuit with a cascode differential amplifier.<
High-speed Level Converter Circuit
Direct Column-sensing Circuit
Cascode Differential Amplifier
Bicmos Integrated Circuits
Address Access Time
Bicmos Ecl Ram
Integrated Memory Circuits
Bimos Integrated Circuits
Wired -or Precoder