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Future BiCMOS technology for scaled supply voltage
By: Shukuri, S.; Nagano, T.; Watanabe, A.; Ikeda, T.;
1989 / IEEE / 0-7803-0817-4
This item was taken from the IEEE Periodical ' Future BiCMOS technology for scaled supply voltage ' A BiCMOS technology for future scaled supply voltage, V/sub x/, is described. Delay time reduction by around 100 ps is achieved by introducing a proposed base electrode surround emitter transistor (BEST). Two types of gates, CBiCMOS and BiNMOS, provide shorter gate delays and higher drivabilities than the CMOS gate even with V/sub s/, of 3.3 V. It is concluded that the innovations in the bipolar transistor structure BEST and in the CBiCMOS and BiNMOS gate circuit configuration are highly promising in comparison to CMOS ULSIs for future high-speed and high-density ULSIs operating at scaled supply voltages.<
Delay Time Reduction
Scaled Supply Voltage
Base Electrode Surround Emitter Transistor
Shorter Gate Delays
Binmos Gate Circuit Configuration
Bicmos Integrated Circuits
Ultra Large Scale Integration
Integrated Circuit Technology
Bimos Integrated Circuits