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A new stacked capacitor DRAM cell characterized by a storage capacitor on a bit-line structure
By: Itoh, K.; Kure, T.; Kawamoto, Y.; Kimura, S.; Hasegawa, N.; Sunami, H.; Takeda, E.; Aoki, M.; Etoh, J.;
1988 / IEEE
This item was taken from the IEEE Periodical ' A new stacked capacitor DRAM cell characterized by a storage capacitor on a bit-line structure ' The authors introduce a diagonal active stacked capacitor cell with a highly packed storage node (DASH) for use in a 16-Mb DRAM (dynamic random access memory). This novel cell features a storage capacitor formed above a bit line and the diagonal active area, which provides a large storage capacitance, 35 fF/bit, in a cell size of 3.4 mu m/sup 2/. The average charge retention time measured using an experimental 2-kb array is 30 s at 40 degrees C, indicating that the DASH has a superior potential for application to 16-Mb DRAMs. The memory cell leakage current is controlled to the order of 10/sup -12/ A.<
Diagonal Active Stacked Capacitor Cell
Dynamic Random Access Memory
Charge Retention Time
Memory Cell Leakage Current
Random Access Memory
Stacked Capacitor Dram Cell
Integrated Memory Circuits
Integrated Circuit Technology
Cmos Integrated Circuits
Highly Packed Storage Node