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A 25 mu m/sup 2/, new poly-Si PMOS load (PPL) SRAM cell having excellent soft error immunity

By: Takeda, E.; Shimohigashi, K.; Sakai, Y.; Ishibashi, K.; Yamanaka, T.; Shimuzu, A.; Nishida, T.; Hashimoto, N.; Hashimoto, T.;

1988 / IEEE

Description

This item was taken from the IEEE Periodical ' A 25 mu m/sup 2/, new poly-Si PMOS load (PPL) SRAM cell having excellent soft error immunity ' A 25- mu m/sup 2/ poly-Si PMOS load SRAM (static random access memory) cell, called a PPL cell, has been developed. The cell has been excellent retention characteristics, high soft-error immunity, and low standby power. These advantages are achieved using poly-Si PMOS loads and cross-coupled stacked capacitors formed between the NMOS and the stacked poly-Si PMOS. A large poly-Si PMOS ON current lowers retention voltage to less than 0.5 V and the soft error rate (SER) under high-speed operation by about an order of magnitude. A 5-fF cross-coupled capacitor improves the retention mode SER by more than an order of magnitude and low standby power is attained with a 0.1-pA OFF current of the poly-Si PMOS. The performance has been evaluated using a 4-kbit SRAM. The cell area has been reduced to 25.38 mu m/sup 2/ using half-micron CMOS technology.<>