Your Search Results

Use this resource - and many more! - in your textbook!

AcademicPub holds over eight million pieces of educational content for you to mix-and-match your way.

Experience the freedom of customizing your course pack with AcademicPub!
Not an educator but still interested in using this content? No problem! Visit our provider's page to contact the publisher and get permission directly.

Architecture of the WE32200 chip set

By: Ng, B.; Cruz-Rios, J.; Nelson, M.S.; Wu, W.S.;

1988 / IEEE / 0-8186-0828-5


This item was taken from the IEEE Periodical ' Architecture of the WE32200 chip set ' Four members of the WE32200 chip set are described. They are the WE32200 central processing unit (CPU), the WE32201 memory management unit (MMU), the WE32204 direct memory access controller (DMAC), and the WE32206 math acceleration unit (MAU). These chips constitute the VLSI core of a general-purpose computing environment supporting virtual memory and IEEE standard floating point arithmetic. The internal architecture of the microprocessor is presented, and the novel features of the four units are examined.<>