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Orthogonal chip mount - A 3D hybrid wafer scale integration technology
By: Stierman, R.J.; Davis, H.E.; Malhi, S.D.S.; Chatterjee, P.K.; Driscoll, C.C.; Bean, K.E.;
1987 / IEEE
Description
This item was taken from the IEEE Periodical ' Orthogonal chip mount - A 3D hybrid wafer scale integration technology ' In the last decade, device scaling in the integrated circuit technology has permitted a drastic improvement in the density of electronic systems. This trend will continue in the next decade. However, submicron feature sizes involved will demand escalating investment in manufacturing equipment and facilities. MOS technology will also reach its fundamental scaling limit at around 0.2 �m. At this time it is necessary that alternative schemes of system density improvement, which are more cost-effective, be explored. Three-dimensional (3D) hybrid wafer scale integration technologies offer this possibility. Such a novel approach, called Orthogonal Chip Mount (OCM), is introduced and described in this paper.
Related Topics
Thermal Conductivity
Resistors
Process Design
Silicon Carbide
Packaging
Integrated Circuit Technology
Diodes
Testing
Wafer Scale Integration
Engineering
Integrated Circuit Interconnections
