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A 32b microprocessor with on-chip 2Kbyte instruction cache
By: Horowitz, M.; Hennessy, J.; Wing, M.; Tjiang, S.; Steenkiste, P.; Stark, D.; Chow, P.; Gulak, P.; Acken, J.; Agarwal, A.; Chorng-Yeung Chu; McFarling, S.; Przybylski, S.; Richardson, S.; Salz, A.; Simoni, R.;
1987 / IEEE
This item was taken from the IEEE Periodical ' A 32b microprocessor with on-chip 2Kbyte instruction cache ' A Reduced Instruction Set Computer with a 5-stage pipeline implemented with 150K transistors on an 8mm�.5mm chip in a 2�m, 2 layer metal CMOS process, will be reported. At operational frequency of 20MHz, a 12MIPS performance has been achieved.