Your Search Results

Use this resource - and many more! - in your textbook!

AcademicPub holds over eight million pieces of educational content for you to mix-and-match your way.

Experience the freedom of customizing your course pack with AcademicPub!
Not an educator but still interested in using this content? No problem! Visit our provider's page to contact the publisher and get permission directly.

A 32b microprocessor with on-chip 2Kbyte instruction cache

By: Horowitz, M.; Hennessy, J.; Wing, M.; Tjiang, S.; Steenkiste, P.; Stark, D.; Chow, P.; Gulak, P.; Acken, J.; Agarwal, A.; Chorng-Yeung Chu; McFarling, S.; Przybylski, S.; Richardson, S.; Salz, A.; Simoni, R.;

1987 / IEEE


This item was taken from the IEEE Periodical ' A 32b microprocessor with on-chip 2Kbyte instruction cache ' A Reduced Instruction Set Computer with a 5-stage pipeline implemented with 150K transistors on an 8mm�.5mm chip in a 2�m, 2 layer metal CMOS process, will be reported. At operational frequency of 20MHz, a 12MIPS performance has been achieved.