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High speed BiCMOS VLSI technology with buried twin well structure

By: Tamba, N.; Watanabe, A.; Ogiue, K.; Odaka, M.; Ikeda, T.; Nishio, Y.; Momma, N.; Nagano, T.;

1985 / IEEE

Description

This item was taken from the IEEE Periodical ' High speed BiCMOS VLSI technology with buried twin well structure ' Bipolar transistors of high cut off frequency (f_{T}=9GHz) and small size have been fabricated on the same chip with a standard CMOS using the buried twin well structure. 1.3 �m LDD CMOS FETs were formed in the thin epitaxial layer(1-1.5�m) with the buried twin well, without degrading the device characteristics of the MOS FET. Ring oscillators of the BiCMOS gate have been fabricated. A 0.4ns gate delay time at 0.6pF and 3.5 times larger driveability than that of the same area CMOS gate were obtained.