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High-speed latchup-free 0.5-µm-channel CMOS using self-aligned TiSi2and deep-trench isolation technologies

By: Park, H.K.; Kawamoto, G.H.; Morimoto, S.; Yamaguchi, T.; Eiden, G.C.;

1983 / IEEE

Description

This item was taken from the IEEE Periodical ' High-speed latchup-free 0.5-µm-channel CMOS using self-aligned TiSi2and deep-trench isolation technologies ' A scaling study showed that a deeper n-well allows lower n-well surface concentration with improved short-channel effects in submicrometer-channel PMOS-FETs. However, the deep n-well leads to poor device-to-device isolation and to poor integration density. The deep-trench isolation combined with an epitaxial layer resolves this drawback and significantly improves Iatchup susceptibility. The sheet resistances of n+- and p+-diffusion and n+- doped polysilicon layers are reduced to 3-4�� by using the self-aligned TiSi2layer with the oxide side-wall spacer. As a result of the deep-trench isolation combined with an epitaxial layer and the self-aligned TiSi2layer, the 0.5 �m-channel CMOS devices operated at a propagation delay time of 140 psec with a power dissipation of 1.5 mW per inverter and attained a maximum clock frequency of 400 MHz in a static � 4 counter without suffering from latchup even at a latchup trigger current of 200 mA.