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Design and fabrication of p-channel FET for 1-µm CMOS technology

By: Hu, G.J.; Dennard, R.H.; Taur, Y.; Ting, C.Y.;

1982 / IEEE

Description

This item was taken from the IEEE Periodical ' Design and fabrication of p-channel FET for 1-µm CMOS technology ' A retrograde n-well is shown to be good for 1-�m bulk CMOS technology using n+polysilicon gates. P-Channel FET's with a threshold voltage of -0.6V fabricated in a retrograde n-well show small short-channel threshold lowering and good turn-off characteristics. In these devices thermally formed TiSi2is self-aligned to the shallow (0.3 �m) source/drain region to reduce the sheet resistance to 4 ohms/square. Because contact resistance from TiSi2to p+is a dominant factor in the total parasitic resistance from metal to the FET channels, high surface doping concentration of S/D regions is still preferred.