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A CMOS LSI 16×16 multiplier/multiplier-accumulator

By: Allen, R.; Troutman, B.; Anderson, J.;

1982 / IEEE

Description

This item was taken from the IEEE Periodical ' A CMOS LSI 16×16 multiplier/multiplier-accumulator ' Two 2� CMOS LSI chips with multiply times less than 100ns, and dissipation of 150mW, will be discussed. The use of Booth's algorithm speeds the multiplication process since the multiplier word is essentially recoded into 8 digits.