Your Search Results

Use this resource - and many more! - in your textbook!

AcademicPub holds over eight million pieces of educational content for you to mix-and-match your way.

Experience the freedom of customizing your course pack with AcademicPub!
Not an educator but still interested in using this content? No problem! Visit our provider's page to contact the publisher and get permission directly.

A CMOS LSI 16×16 multiplier/multiplier-accumulator

By: Allen, R.; Troutman, B.; Anderson, J.;

1982 / IEEE


This item was taken from the IEEE Periodical ' A CMOS LSI 16×16 multiplier/multiplier-accumulator ' Two 2� CMOS LSI chips with multiply times less than 100ns, and dissipation of 150mW, will be discussed. The use of Booth's algorithm speeds the multiplication process since the multiplier word is essentially recoded into 8 digits.