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A 32 nm, 3.1 Billion Transistor, 12 Wide Issue Itanium� Processor for Mission-Critical Servers

By: Riedlinger, R.; Stefaniw, M.W.; Biro, L.; Bowhill, B.; Crop, J.; Duda, K.; Fetzer, E.S.; Franza, O.; Grutkowski, T.; Little, C.; Morganti, C.; Moyer, G.; Munch, A.; Nagarajan, M.; Parks, C.; Poirier, C.; Repasky, B.; Roytman, E.; Singh, T.; Arnold, R.;

2012 / IEEE

Description

This item was taken from the IEEE Periodical ' A 32 nm, 3.1 Billion Transistor, 12 Wide Issue Itanium� Processor for Mission-Critical Servers ' An Itanium� processor implemented in 32 nm CMOS with nine layers of Cu contains 3.1 billion transistors. The die measures 18.2 mm by 29.9 mm. The processor has eight multi-threaded cores, a ring based system interface and combined cache on the die is 50 MB. High-speed links allow for peak processor-to-processor bandwidth of up to 128 GB/s and memory bandwidth of up to 45 GB/s.