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A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and `1'/`0' Dual-Array Equalized Reference Scheme

By: Matsuoka, H.; Ohno, H.; Ikeda, S.; Takahashi, H.; Ito, K.; Yamanouchi, M.; Ono, K.; Matsuzaki, N.; Hayakawa, J.; Yamamoto, H.; Miura, K.; Kawahara, T.; Takemura, R.; Hasegawa, H.;

2010 / IEEE

Description

This item was taken from the IEEE Periodical ' A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and `1'/`0' Dual-Array Equalized Reference Scheme ' A 32-Mb SPin-transfer torque RAM (SPRAM) chip was demonstrated with an access time of 32 ns and a cell write-time of 40 ns at a supply voltage of 1.8 V. The chip was fabricated with 150-nm CMOS and a 100 × 200-nm tunnel magneto-resistive (TMR) device element. A required thermal stability of 67 of the TMR device was estimated by taking into account the disturbances during read operations and data retention periods of 10 years for nonvolatile operation. The 32-Mb SPRAM chip features three circuit technologies suitable for a large-scale array: 1) a two-transistor, one-resistor (2T1R) type memory cell for achieving a sufficiently large write current despite the small cell size, 2) a compact read/write separated hierarchy bit/source-line structure with a localized bi-directional write driver for efficiently distributing write current, and 3) a '1'/'0' dual-array equalized reference scheme for stable read operation.