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Time Dependence of Bias-Stress-Induced SiC MOSFET Threshold-Voltage Instability Measurements
2008 / IEEE
This item was taken from the IEEE Periodical ' Time Dependence of Bias-Stress-Induced SiC MOSFET Threshold-Voltage Instability Measurements ' We have observed significant instability in the threshold voltage of 4H-SiC metal-oxide-semiconductor field-effect transistors due to gate-bias stressing. This effect has a strong measurement time dependence. For example, a 20-mus-long gate ramp used to measure the I-V characteristic and extract a threshold voltage was found to result in a instability three to four times greater than that measured with a 1-s-long gate ramp. The VT instability was three times greater in devices that did not receive a NO postoxidation anneal compared with those that did. This instability effect is consistent with electrons directly tunneling in and out of near-interfacial oxide traps, which in irradiated Si MOS was attributed to border traps.
Bias-stress-induced Sic Mosfet
Threshold-voltage Instability Measurements
Metal-oxide-semiconductor Field-effect Transistors
No Postoxidation Anneal
Oxide Charge Trapping
Silicon Carbide (sic)
Monolithic Integrated Circuits
Wide Band Gap Semiconductors
Engineered Materials, Dielectrics And Plasmas
Components, Circuits, Devices And Systems