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Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs

By: Yasu, Y.; Mizuno, H.; Kanno, Y.; Irie, N.; Yanagisawa, K.; Hattori, T.; Hirose, K.; Irita, T.; Yamada, T.; Ishii, T.; Miyairi, Y.; Hoshi, T.; Shimazaki, Y.;

2007 / IEEE

Description

This item was taken from the IEEE Periodical ' Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs ' Hierarchical power distribution with a power tree has been developed. The key features are a power-tree structure with three power-tree management rules and a distributed common power domain implementation. The hierarchical power distribution supports a fine-grained power gating with dozens of power domains, which is analogous to a fine-grained clock gating. Leakage currents of a 1 000 000-gate power domain were effectively reduced to 1/4000 in multi-CPU SoCs with minimal area overhead