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A 512-mb DDR3 SDRAM prototype with C/sub IO/ minimization and self-calibration techniques

By: HoeJu Chung; Yun-Sang Lee; Soo-In Cho; Changhyun Kim; Jung-Bae Lee; Kyu-Hyoun Kim; Ki-Whan Song; Seunghoon Lee; Jin-Hyung Cho; Churoo Park; Jun-Ho Shin; Taek-Seon Park; Seung-young Seo; Sung-Ho Choi; Dae-Hee Jung; Moo-Sung Chae; JaeJun Lee; Jaekwan Kim;

2006 / IEEE

Description

This item was taken from the IEEE Periodical ' A 512-mb DDR3 SDRAM prototype with C/sub IO/ minimization and self-calibration techniques ' A 1.5-V 512-Mb DDR3 synchronous DRAM prototype was designed and fabricated in 80-nm technology. Critical to the signal integrity in DDR3 point-to-2points (P22P) interfacing is an efficient calibration scheme and C/sub IO/ minimization, which were achieved by on-die-termination (ODT)-merged output drivers, SCR type ESD protection, and self-calibration scheme. The hybrid latency control scheme can turn the DLL off in standby mode, reducing power consumption. User-friendly functions such as temperature read-out from on-chip sensor and per-bank-refresh were also implemented.