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Highly manufacturable advanced gate-stack technology for sub-45-nm self-aligned gate-first CMOSFETs

By: Zhibo Zhang; Seung-Chul Song; Byoung Hun Lee; Moumen, N.; Sim, J.H.; Huffman, C.; Majhi, P.; Kirsch, P.D.; Sang Ho Bae; Rino Choi;

2006 / IEEE


This item was taken from the IEEE Periodical ' Highly manufacturable advanced gate-stack technology for sub-45-nm self-aligned gate-first CMOSFETs ' Issues surrounding the integration of Hf-based high-/spl kappa/ dielectrics with metal gates in a conventional CMOS flow are discussed. The careful choice of a gate-stack process as well as optimization of other CMOS process steps enable robust metal/high-/spl kappa/ CMOSFETs with wide process latitude. HfO/sub 2/ of a 2-nm physical thickness shows a very minimal transient charge trapping resulting from kinetically suppressed crystallization. Thickness of metal electrode is also a critical factor to optimize physical-stress effects and minimize dopant diffusion. A high-temperature anneal after source/drain implantation in a conventional CMOSFET process is found to reduce the interface state density and improve the electron mobility. Even though MOSFET process using single midgap metal gate addresses fundamental issues related to implementing metal/high-/spl kappa/ stack, integrating two different metals on the same wafer (i.e., dual metal gate) poses several additional challenges, such as metal gate separation between n- and pMOS and gate-stack dry etch. We demonstrate that a dual metal gate CMOSFET yields high-performance devices even with a conventional gate-first approach if an appropriate metal separation between band-edge metal for nMOS and pMOS is incorporated. Optimization of dry-etch process enables gentle and complete removal of two different metal gate stacks on ultrathin high-/spl kappa/ layer.