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Fabrication and mobility characteristics of SiGe surface channel pMOSFETs with a HfO/sub 2//TiN gate stack
By: Ernst, T.; Weber, O.; Ducroquet, F.; Andrieu, F.; Damlencourt, J.-F.; Hartmann, J.-M.; Deleonibus, S.; Guillaumot, B.; Renault, O.; Papon, A.-M.;
2006 / IEEE
This item was taken from the IEEE Periodical ' Fabrication and mobility characteristics of SiGe surface channel pMOSFETs with a HfO/sub 2//TiN gate stack ' This paper describes an extensive experimental study of TiN/HfO/sub 2//SiGe and TiN/HfO/sub 2//Si cap/SiGe gate stacked-transistors. Through a careful analysis of the interface quality (interface states and roughness), we demonstrate that an ultrathin silicon cap is mandatory to obtain high hole mobility enhancement. Based on quantum mechanical simulations and capacitance-voltage characterization, we show that this silicon cap is not contributing any silicon parasitic channel conduction and degrades by only 1 /spl Aring/ the electrical oxide thickness in inversion. Due to this interface optimization, Si/sub 0.72/Ge/sub 0.28/ pMOSFETs exhibit a 58% higher mobility at high effective field (1 MV/cm) than the universal SiO/sub 2//Si reference and a 90% higher mobility than the HfO/sub 2//Si reference. This represents one of the best hole mobility results at 1 MV/cm ever reported with a high-/spl kappa//metal gate stack. We thus validate a possible solution to drastically improve the hole mobility in Si MOSFETs with high-/spl kappa/ gate dielectrics.
Gate Stacked Transistors
Quantum Mechanical Simulations
Parasitic Channel Conduction
High-k Gate Dielectrics
Charge Carrier Mobility
High-k Dielectric Thin Films
Engineered Materials, Dielectrics And Plasmas
Components, Circuits, Devices And Systems