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Compact modeling of a flash memory cell including substrate-bias-dependent hot-electron gate current
By: Shimizu, S.; Tanizawa, M.; Sonoda, K.; Kotani, N.; Ohji, Y.; Inoue, Y.; Araki, Y.; Eimori, T.; Ishikawa, K.; Kobayashi, S.; Ogura, T.; Kawai, S.;
2004 / IEEE
This item was taken from the IEEE Periodical ' Compact modeling of a flash memory cell including substrate-bias-dependent hot-electron gate current ' We propose a compact model for a Flash memory cell that is suitable for circuit simulation. The model includes a hot-electron gate current model that considers not only channel hot electron injection but also channel initiated secondary electron injection to express properly substrate bias dependence of gate current. Tunneling gate current for erasing is expressed by the BSIM4 tunneling gate current model. Good agreement between measured and simulated results of both programming and erasing characteristics for 130-nm technology Flash memory cells indicates that our model is useful in designing and optimizing circuit for Flash memories.
Hot-electron Gate Current Model
Channel Hot Electron Injection
Channel Initiated Secondary Electron Injection
Substrate Bias Dependence
Bsim4 Tunneling Gate Current Model
Integrated Circuit Modeling
Substrate-bias-dependent Hot-electron Gate Current
Flash Memory Cell
Integrated Circuit Modelling
Hot Electron Transistors
Engineered Materials, Dielectrics And Plasmas
Components, Circuits, Devices And Systems