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A transition-encoded dynamic bus technique for high-performance interconnects

By: Rai, N.; Anders, M.; Borkar, S.; Krishnamurthy, R.K.;

2003 / IEEE

Description

This item was taken from the IEEE Periodical ' A transition-encoded dynamic bus technique for high-performance interconnects ' This paper describes a transition-encoded dynamic bus technique that enables on-chip interconnect delay reduction while maintaining the robustness and switching energy behavior of a static bus. Efficient circuits, designed for a drop-in replacement, enable significant delay and peak-current reduction even for short-length buses, while obtaining energy savings at aggressive delay targets. On a 180-nm 32-bit microprocessor, 79% of all global buses exhibit 10%-35% performance improvement using this technique.