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A system LSI memory redundancy technique using an ie-flash (inverse-gate-electrode flash) programming circuit

By: Yanagisawa, K.; Yamaoka, M.; Ishibashi, K.; Norisue, K.; Shukuri, S.;

2002 / IEEE

Description

This item was taken from the IEEE Periodical ' A system LSI memory redundancy technique using an ie-flash (inverse-gate-electrode flash) programming circuit ' A new memory redundancy technique using inverse-gate-electrode flash (ie-flash) memory cells has been developed. The ie-flash can be fabricated by the conventional logic CMOS process, so no additional processes are necessary in using it in system LSIs, and it can be programmed by logic testers. We enhanced the reliability of ie-flash by using some circuits, increasing reliability to endure practical use. This new redundancy technique was successfully implemented in the cache memories of a 32-b RISC microprocessor.