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The physical and electrical effects of metal-fill patterning practices for oxide chemical-mechanical polishing processes
By: Stine, B.E.; Kapoor, A.; Berman, M.; Towery, D.; Muthukrishnan, M.; Chung, J.E.; Boning, D.S.; Loh, W.; Equi, E.R.; Kruppa, F.; Camilletti, L.; Prasad, S.;
1998 / IEEE
This item was taken from the IEEE Periodical ' The physical and electrical effects of metal-fill patterning practices for oxide chemical-mechanical polishing processes ' In oxide chemical-mechanical polishing (CMP) processes, layout pattern dependent variation in the interlevel dielectric (ILD) thickness can reduce yield and impact circuit performance. Metal-fill patterning practices have emerged as a technique for substantially reducing layout pattern dependent ILD thickness variation. We present a generalizable methodology for selecting an optimal metal-fill patterning practice with the goal of satisfying a given dielectric thickness variation specification while minimizing the added interconnect capacitance associated with metal-fill patterning. Data from two industrial-based experiments demonstrate the beneficial impact of metal-fill on dielectric thickness variation, a 20% improvement in uniformity in one case and a 60% improvement in the other case, and illustrate that pattern density is the key mechanism involved. The pros and cons of two different metal-fill patterning practices-grounded versus floating metal-are explored. Criteria for minimizing the effect of floating or grounded metal-fill patterns on delay or crosstalk parameters are also developed based on canonical metal-fill structures. Finally, this methodology is illustrated using a case study which demonstrates an 82% reduction in ILD thickness variation.
Large Scale Integration
Integrated Circuit Interconnections
Integrated Circuit Yield
Interlevel Dielectric Thickness
Layout Pattern Dependence
Engineered Materials, Dielectrics And Plasmas
Components, Circuits, Devices And Systems
Oxide Chemical-mechanical Polishing