Your Search Results

Use this resource - and many more! - in your textbook!

AcademicPub holds over eight million pieces of educational content for you to mix-and-match your way.

Experience the freedom of customizing your course pack with AcademicPub!
Not an educator but still interested in using this content? No problem! Visit our provider's page to contact the publisher and get permission directly.

CMOS scaling into the nanometer regime

By: Wind, S.J.; Wann, H.-J.C.; Viswanathan, R.G.; Sai-Halasz, G.A.; Shih-Hsien Lo; Hon-Sum Wong; Frank, D.J.; Wei Chen; Buchanan, D.A.; Yuan Taur; Ismail, K.E.;

1997 / IEEE

Description

This item was taken from the IEEE Periodical ' CMOS scaling into the nanometer regime ' Starting with a brief review on 0.1-/spl mu/m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFET's, low-temperature CMOS, and double-gate MOSFET's, which may lead to the outermost limits of silicon scaling.