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Driving source-line cell architecture for sub-1-V high-speed low-power applications
By: Nagano, T.; Mizuno, H.;
1996 / IEEE
This item was taken from the IEEE Periodical ' Driving source-line cell architecture for sub-1-V high-speed low-power applications ' A novel SRAM cell architecture for sub-1-V high-speed operation is proposed that uses neither low-V/sub th/ MOSFETs nor modified cell layout patterns. A source-line, connected to the source terminals of the driver MOSFETs is controlled so that it is negative and floating in the read and write cycles, respectively. This improved the bit-line access time by 1/4-1/2 at supply voltages of 0.5-1.0 V. Limiting the bit-line swing reduces by 1/10 the writing power needed to charge them and allows faster write-recovery, as well. The achievability of low-power 100-MHz operation over a wide range of supply voltages is demonstrated.
Cmos Memory Circuits
Driving Source-line Cell Architecture
Sram Cell Architecture
Bit-line Access Time
0.5 To 1 V
Large Scale Integration
Random Access Memory
Engineered Materials, Dielectrics And Plasmas
Components, Circuits, Devices And Systems