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Low-power chip interconnection by dynamic termination

By: Kimura, K.; Sekiguchi, T.; Etoh, J.; Horiguchi, M.; Kawahara, T.; Aoki, M.;

1995 / IEEE

Description

This item was taken from the IEEE Periodical ' Low-power chip interconnection by dynamic termination ' A low-power dynamic termination scheme is proposed and demonstrated as a way to reduce power dissipation for high-speed data transport. In this scheme, the transmission lines are terminated only if the signals change. The gate of a switching MOS transistor connected to a termination resistor is driven by differentiating the transmission signal with a resistor and a capacitor. The power dissipation of the terminating resistor can be reduced to 1/5 in the conventional determination scheme, and overshoot can be reduced to 1/5 that in the open scheme. This scheme is promising for use with palm-top equipment, facilitating high-speed low power operation.<>