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A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers

By: Komiyaji, K.; Takasugi, K.; Ishibashi, K.; Nishida, T.; Nagano, T.; Hashimoto, T.; Toyoshima, H.; Shimizu, A.; Ohki, N.; Hashimoto, N.; Fukami, A.; Yamanaka, T.;

1995 / IEEE

Description

This item was taken from the IEEE Periodical ' A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers ' A 4-Mb CMOS SRAM with 3.84 /spl mu/m/sup 2/ TFT load cells is fabricated using 0.25-/spl mu/m CMOS technology and achieves an address access time of 6 ns at a supply voltage of 2.7 V. The use of a current sense amplifier that is insensitive to its offset voltage enables the fast access time. A boosted cell array architecture allows low voltage operation of fast SRAM's using TFT load cells.<>