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A 35 ns cycle time 3.3 V only 32 Mb NAND flash EEPROM
By: Oodaira, H.; Nakamura, H.; Sugiura, Y.; Imamiya, K.; Iwata, Y.; Miyamoto, J.-I.; Momodomi, M.; Narita, K.; Masuda, K.; Araki, H.; Watanabe, T.; Itoh, Y.;
1995 / IEEE
This item was taken from the IEEE Periodical ' A 35 ns cycle time 3.3 V only 32 Mb NAND flash EEPROM ' A 32 Mb NAND type flash EEPROM has been developed with 0.425 /spl mu/m CMOS technology. A 35 ns cycle time is achieved by adopting a pipeline scheme. A boosted word-line scheme and a program verify operation achieving tight threshold voltage (Vth) distribution of programmed cells reduce read-out access time. Multiple block erase operation is realized by adopting erase block registers. All functions are operable with a single 5.3 V or 5 V power supply.
Read-out Access Time
Multiple Block Erase Operation
Erase Block Registers
Cmos Logic Circuits
Semiconductor Device Noise
Threshold Voltage Distribution
Program Verify Operation
Boosted Word-line Scheme
Nand Flash Eeprom
Cmos Memory Circuits
Engineered Materials, Dielectrics And Plasmas
Components, Circuits, Devices And Systems