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A 300-MHz 4-Mb wave-pipeline CMOS SRAM using a multiphase PLL

By: Yamanaka, T.; Ishida, H.; Ohki, N.; Minami, R.; Nagano, T.; Komiyaji, K.; Ishibashi, K.; Toyoshima, H.; Nishida, T.;

1995 / IEEE

Description

This item was taken from the IEEE Periodical ' A 300-MHz 4-Mb wave-pipeline CMOS SRAM using a multiphase PLL ' A 4-Mb (64 k/spl times/64) synchronous wave-pipeline CMOS SRAM is fabricated by 0.25-/spl mu/m CMOS technology. Multiphase active pulse control (MPAC) enables fully random 300 MHz operation at 2.5 V, resulting in a bandwidth of 2.4 GB/s. The pulse is generated by multiphase PLL (MPPLL) using an array oscillator with current consumption of 7.5 mA.