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Advanced TFT SRAM cell technology using a phase-shift lithography

By: Sasaki, K.; Ishibashi, K.; Mine, T.; Takeda, E.; Nagano, T.; Nishida, T.; Ohki, N.; Shimizu, A.; Hashimoto, N.; Tanaka, T.; Hasegawa, N.; Hashimoto, T.; Yamanaka, T.;

1995 / IEEE

Description

This item was taken from the IEEE Periodical ' Advanced TFT SRAM cell technology using a phase-shift lithography ' An advanced TFT memory cell technology has been developed for making high-density and high-speed SRAM cells. The cell is fabricated using a phase-shift lithography that enables patterns with spaces of less than 0.25 /spl mu/m to be made using the conventional stepper. Cell area is also reduced by using a small cell-ratio and a parallel layout for the transistor. Despite the small cell-ratio, stable operation is assured by using advanced polysilicon PMOS TFT's for load devices. The effect of the Si/sub 3/N/sub 4/ multilayer gate insulator on the on-current and the influence of the channel implantation are also investigated. To obtain stable operation and extremely low stand-by power dissipation, a self-aligned offset structure for the polysilicon PMOS TFT is proposed and demonstrated. A leakage current of only 2 fA/cell and an on-/off-current ratio of 4.6/spl times/10/sup 6/ are achieved with this polysilicon PMOS TFT in a memory cell, which is demonstrated in a experimental 1-Mbit CMOS SRAM chip that has an access time of only 7 ns.<>