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A 9-ns 16-Mb CMOS SRAM with offset-compensated current sense amplifier

By: Seno, K.; Kobayashi, K.; Chuang, P.T.; Tomo, Y.; Sasaki, M.; Shu, L.-L.; Knorpp, K.; Miyaji, F.; Sato, H.; Kihara, H.; Teshima, N.; Takeda, M.;

1993 / IEEE

Description

This item was taken from the IEEE Periodical ' A 9-ns 16-Mb CMOS SRAM with offset-compensated current sense amplifier ' A 9-ns 16-Mb CMOS SRAM has been developed using a 0.35- mu m CMOS process, The current-mode fully nonequalized data path has been realized in a CMOS SRAM for the first time by using a stabilized feedback current-sense amplifier (SFCA) that provides a small input resistance and an offset compensation effect. To reduce the test time, a bit-line wired-OR parallel test circuit has been implemented.<>