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An experimental 1.5-V 64-Mb DRAM
By: Kawamoto, Y.; Murai, F.; Watanabe, Y.; Kume, E.; Takeuchi, K.; Tanaka, H.; Nakagome, Y.; Itoh, K.; Takeda, E.; Nishida, T.; Kaga, T.; Kisu, T.; Hisamoto, D.; Izawa, R.;
1991 / IEEE
This item was taken from the IEEE Periodical ' An experimental 1.5-V 64-Mb DRAM ' Low-voltage circuit technologies for higher-density dynamic RAMs (DRAMs) and their application to an experimental 64-Mb DRAM with a 1.5-V internal operating voltage are presented. A complementary current sensing scheme is proposed to reduce data transmission delay. A speed improvement of 20 ns was achieved when utilizing a 1.5-V power supply. An accurate and speed-enhanced half-V/sub CC/ voltage generator with a current-mirror amplifier and tri-state buffer is proposed. With it, a response time reduction of about 1.5 decades was realized. A word-line driver with a charge-pump circuit was developed to achieve a high boost ratio. A ratio of about 1.8 was obtained from a power supply voltage as low as 1.0 V. A 1.28 mu m/sup 2/ crown-shaped stacked-capacitor (CROWN) cell was also made to ensure a sufficient storage charge and to minimize data-line interference noise. An experimental 1.5 V 64 Mb DRAM was designed and fabricated with these technologies and 0.3 mu m electron-beam lithography. A typical access time of 70 ns was obtained, and a further reduction of 50 ns is expected based on simulation results. Thus, a high-speed performance, comparable to that of 16-Mb DRAMs, can be achieved with a typical power dissipation of 44 mW, one tenth that of 16-Mb DRAMs. This indicates that a low-voltage battery operation is a promising target for future DRAMs.<
Response Time Reduction
Low-voltage Battery Operation
Random Access Memory
Signal To Noise Ratio
Complementary Current Sensing Scheme
Triple Well Cmos
Lv Circuit Technologies
Cmos Integrated Circuits
Engineered Materials, Dielectrics And Plasmas
Components, Circuits, Devices And Systems