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A 23-ns 4-Mb CMOS SRAM with 0.2- mu A standby current

By: Sasaki, K.; Minato, O.; Meguro, S.; Koike, A.; Ikeda, S.; Honjo, S.; Moriwake, N.; Yamanaka, T.; Shimohigashi, K.; Ishibashi, K.;

1990 / IEEE

Description

This item was taken from the IEEE Periodical ' A 23-ns 4-Mb CMOS SRAM with 0.2- mu A standby current ' A 4-Mb CMOS SRAM having 0.2- mu A standby current at a supply voltage of 3 V has been developed. Current-mirror/PMOS cross-coupled cascade sense-amplifier circuits have achieved the fast address access time of 23 ns. A new noise-immune data-latch circuit has attained power-reduction characteristics at a low operating cycle time without access delay. A 0.5- mu m CMOS, four-level poly, two-level metal technology with a polysilicon PMOS load memory cell, yielded a small cell area of 17 mu m/sup 2/ and the very small standby current. A quadruple-array, word-decoder architecture allowed a small chip area of 122 mm/sup 2/.<>