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An 80-ns 1-Mb flash memory with on-chip erase/erase-verify controller

By: Kobayashi, T.; Ohji, Y.; Kume, H.; Seki, K.; Shoji, K.; Kubota, Y.; Hiraiwa, A.; Nishimoto, T.; Izawa, K.; Komori, K.; Wada, T.; Nishida, T.;

1990 / IEEE

Description

This item was taken from the IEEE Periodical ' An 80-ns 1-Mb flash memory with on-chip erase/erase-verify controller ' An internal erase and erase-verify control system has been implemented in an electrically erasable, reprogrammable, 80-ns 1-Mb flash memory, which is suitable for in-system reprogram applications. The memory utilizes a one-transistor type cell with a cell area of 10.4 mu /sup 2/. The die area is 32.3 mm/sup 2/. An erase mode is initiated by a 50-ns pulse. An erase and erase-verify sequence is automatically conducted in a chip without any further external control. The internal status can be checked through a status-polling mode. The 80-ns access time results from advanced sense amplifiers as well as low-resistance polysilicide word lines and scaled periphery transistors. To realize high-sensitivity, high-speed sense circuits, a pMOS transistor (whose gate is connected to its drain) is used as a load transistor.<>