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A 20 K CMOS array with 200-ps gate delay

By: Nuez, J.-P.; Mollier, P.; Boudon, G.; Ogura, S.; Bhattacharyya, A.; Wallart, F.;

1988 / IEEE

Description

This item was taken from the IEEE Periodical ' A 20 K CMOS array with 200-ps gate delay ' A 20 K NAND2 equivalent CMOS gate array prototype with 0.5- mu m channel length FETs is described. The 7.5*7.5-mm chip is designed for high performance with 200-ps gate delay. Large macros such as a 32-b RISC (reduced instruction-set computer) processor and 128*8 SRAM (static random-access memory) have been implemented with automatic placement and wiring tools. Their respective predicted performances of 17-ns cycle and 6.1-ns access time have been verified. This confirms that the speed of complex functions in half-micrometer-channel-length CMOS technology is getting close to the speed achieved by current bipolar hardware.<>