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A 16-Mbit DRAM with a relaxed sense-amplifier-pitch open-bit-line architecture

By: Yamamoto, H.; Inoue, M.; Odanaka, S.; Ogawa, S.; Fuse, G.; Aoi, N.; Nakao, I.; Ueno, A.; Kubota, M.; Fukumoto, M.; Akamatsu, H.; Matsushima, J.; Fujiwara, A.; Yamauchi, H.; Kotani, H.; Yamada, T.;

1988 / IEEE

Description

This item was taken from the IEEE Periodical ' A 16-Mbit DRAM with a relaxed sense-amplifier-pitch open-bit-line architecture ' A 16-Mb dynamic RAM has been designed and fabricated using 0.5- mu m CMOS technology with double-level metallization. It uses a novel trench-type surrounding high-capacitance cell (SCC) that measures only 3.3- mu m/sup 2/ in cell size with a 63-fF storage capacitance. A novel relaxed sense-amplifier-pitch (RSAP) open-bit-line architecture used on the DRAM achieves a high-density memory cell array, while maintaining a large enough layout pitch for the sense amplifier. These concepts allow the small chip that measures 5.4*17.38 (93.85) mm/sup 2/ to be mounted in a 300-mil dual-in-line package with 65-ns RAS access time and 35-ns column address access time.<>