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Trench transistor DRAM cell
By: Shichijo, H.; Banerjee, S.K.; Chatterjee, P.K.; Shah, A.H.; Davis, H.E.; Gallia, J.; Wang, C.-P.; Elahy, M.; Womack, R.H.; Bordelon, D.M.; Richardson, W.F.; Pollack, G.P.; Malhi, S.D.S.;
1986 / IEEE
This item was taken from the IEEE Periodical ' Trench transistor DRAM cell ' A new one-transistor DRAM cell with both the transistor and the capacitor fabricated on the trench sidewalls is described. With the signal stored on the polysilicon node surrounded by oxide, the cell is expected to have a high alpha particle immunity. The cell occupies only 9 �m2using 1-�m design rules. This cell size is sufficiently small to enable a 4-Mbit DRAM of reasonable chip size with these design rules, and possesses further scalability for 16-Mbit DRAM's.