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Implementation of a 32 Kbit/s ADPCM Codec Using a General-Purpose Digital Signal Processor
By: Matsumura, T.; Murano, K.; Gambe, H.;
1986 / IEEE
This item was taken from the IEEE Periodical ' Implementation of a 32 Kbit/s ADPCM Codec Using a General-Purpose Digital Signal Processor ' This paper describes an implementation of a CCITT G.721 compatible 32kbit/s ADPCM codec, using a general-purpose digital signal processor FDSP-3 (MB8764). A single-channel ADPCM codec is realized by two FDSP-3 chips-one for the encoder and the other for the decoder. Meticulous programming techniques are employed to achieve exact computation of the CCITT algorithm exploiting all the available resources of the 16-bit fixed-point DSP. It is shown that the whole codec computation can be accomplished in about 2350 machine cycles. Thus, two FDSP-3 chips operating at 10 MHz machine cycle can handle the whole computation. The paper also covers the comparison of straight fixed-point format and the G.721 realization, and briefly examines the compatibility issue between these two methods.
Digital Signal Processors
Digital Signal Processing Chips
Signal Processing Algorithms
Random Access Memory
Differential Pulse-code Modulation
Very Large-scale Integration (vlsi)
Communication, Networking And Broadcast Technologies