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Characteristics and Three-Dimensional Integration of MOSFET's in Small-Grain LPCVD Polycrystalline Silicon
By: Sundaresan, R.; Chatterjiee, P.K.; Banerjee, S.K.; Shichijo, H.; Malhi, S.D.S.; Hon Wai Lam; Elahy, M.; Womack, R.H.; Hite, L.R.; Shah, A.H.; Richardson, W.F.; Pollack, G.P.;
1985 / IEEE
This item was taken from the IEEE Periodical ' Characteristics and Three-Dimensional Integration of MOSFET's in Small-Grain LPCVD Polycrystalline Silicon ' Building on nearly two decades of reported results for MOSFET's fabricated in small-grain polycrystalline silicon, a design methodology is developed that yields devices which have low threshold voltage, high drive current, low leakage current, tight parameteric control, and reduced topology, while requiring no nonstandard materials, processes, and tools. Design criteria and device performance are discussed, grain boundary characterization techniques are described, technological issues pertinent to VLSI implementation are investigated, and long-term device reliability is studied. The potential applications of the polysilicon MOSFET's in high-density dRAM and sRAM are explored. The successful implementation of an experimental stacked CMOS 64K static RAM proves the utility of these devices for three-dimensional integration in a VLSI environment.
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