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Author: Von Arnim, K.

Results

Impact of STI-induced stress, inverse narrow width effect, and statistical V/sub TH/ variations on leakage currents in 120 nm CMOS
2004 / IEEE / 0-7803-8478-4
By: Martin, B.; Pacha, C.; Thewes, R.; Berthold, J.; Seegebrecht, P.; Schmitt-Landsiedel, D.; Brederlow, R.; von Arnim, K.;
Efficiency of body biasing in 90 nm CMOS for low power digital circuits
2004 / IEEE / 0-7803-8480-6
By: Thewes, R.; Brederlow, R.; Fiedler, H.; Seegebrecht, P.; Berthold, J.; von Arnim, K.; Borinski, E.; Pacha, C.;
Efficiency of body biasing in 90-nm CMOS for low-power digital circuits
2005 / IEEE
By: Thewes, R.; Brederlow, R.; Seegebrecht, P.; Fiedler, H.; Berthold, J.; Borinski, E.; von Arnim, K.; Pacha, C.;
A low-leakage 2.5GHz skewed CMOS 32b adder for nanometer CMOS technologies
2005 / IEEE / 0-7803-8904-2
By: Thewes, R.; Seegebrecht, P.; von Arnim, K.; Pacha, C.;
Circuit design issues in multi-gate FET CMOS technologies
2006 / IEEE / 1-4244-0079-1
By: Berthold, J.; Russ, C.; Marshall, A.; Knoblinger, G.; Nirschl, T.; Gostkowski, M.; Weize Xiong; Schulz, T.; von Arnim, K.; Pacha, C.; Schruefer, K.; Cleavelin, R.; Patruno, P.; Duvvury, C.; Gossner, H.;
Exploration of the Circuit Potential of Multiple-Gate Field-Effect Transistors
2006 / IEEE / 1-4244-0289-1
By: Augendre, E.; Varela, O.; Ramos, J.; von Arnim, K.; Chiarella, T.; Nackaerts, A.; Severi, S.; Biesemans, S.; Jurczak, M.; Collaert, N.; Hoffmann, T.; Rosmeulen, M.; Kerner, C.;
Circuit Performance of Low-Power Optimized Multi-Gate CMOS Technologies
2007 / IEEE / 1-4244-0584-X
By: Xiong, W.; Schulz, T.; Cleavelin, C.R.; Berthold, J.; Patruno, P.; von Arnim, K.; Schruefer, K.; Pacha, C.;
A Low-Power Multi-Gate FET CMOS Technology with 13.9ps Inverter Delay, Large-Scale Integrated High Performance Digital Circuits and SRAM
2007 / IEEE / 978-4-900784-03-1
By: Degroote, B.; Collaert, N.; Rooyackers, R.; Nackaerts, A.; Vandeweyer, T.; Bauer, F.; San, K.T.; Schulz, T.; Pacha, A.C.; Augendre, E.; von Arnim, K.; Jurczak, M.; Schrufer, K.; Cleavelin, C.R.; Marshall, A.; Xiong, W.; Singanamalla, R.; Dixit, A.;
An Effective Switching Current Methodology to Predict the Performance of Complex Digital Circuits
2007 / IEEE / 978-1-4244-1507-6
By: Pacha, C.; von Arnim, K.; Berthold, J.; Schriifer, K.; Schulz, T.; Hofmann, K.;
Efficiency of low-power design techniques in Multi-Gate FET CMOS Circuits
2007 / IEEE / 978-1-4244-1125-2
By: Cleavelin, C.-R.; Baumann, T.; Marshall, A.; San, K.T.; Xiong, W.; Schruefer, K.; Schulz, T.; Bauer, F.; von Arnim, K.; Pacha, C.; Berthold, J.;
Layout options for stability tuning of SRAM cells in multi-gate-FET technologies
2007 / IEEE / 978-1-4244-1125-2
By: Fulde, M.; Schulz, T.; Schmitt-Landsiedel, D.; Pacha, C.; von Arnim, K.; Bauer, F.; Nackaerts, A.; Georgakos, G.; Schrufer, K.; Cleavelin, C.-R.; San, K.T.; Xiong, W.; Jurczak, M.;
Analog design challenges and trade-offs using emerging materials and devices
2007 / IEEE / 978-1-4244-1123-8
By: Subramanian, V.; Parvais, B.; Gustin, C.; Mercha, A.; Fulde, M.; von Arnim, K.; Schmitt-Landsiede, D.; Knoblinger, G.; Schruefer, K.; Bauer, F.;
Multi-gate devices for the 32nm technology node and beyond
2007 / IEEE / 978-1-4244-1123-8
By: Pawlak, B.J.; Rooyackers, R.; Mercha, A.; Lenoble, D.; Lai, L.-S.; Ferain, I.; Dixit, A.; De Keersgieter, A.; Collaert, N.; Nackaerts, A.; Jurczak, M.; Biesemans, S.; De Meyer; Witters, L.; von Arnim, K.; Verheyen, P.; Van Dal, M.J.H.; Son, N.J.; Sar, K.T.; Schulz, T.;
Low-voltage 6T FinFET SRAM cell with high SNM using HfSiON/TiN gate stack, fin widths down to 10nm and 30nm gate length
2008 / IEEE / 978-1-4244-1810-7
By: Witters, L.; Nackaerts, A.; Mercha, A.; Parvais, B.; Vandeweyer, T.; Rooyackers, R.; von Arnim, K.; Collaert, N.; Jurczak, M.; Biesemans, S.; De Meyer, K.; Veloso, A.; Ferain, I.; Bauer, F.; Devriendt, K.; Demuynck, S.; Hikavyy, A.; Demand, M.; Altamirano Sanchez, E.;
High-�/metal gate low power bulk technology - Performance evaluation of standard CMOS logic circuits, microprocessor critical path replicas, and SRAM for 45nm and beyond
2009 / IEEE / 978-1-4244-2784-0
By: Park, D.-G.; Stein, K.; Khare, M.; Divakaruni, R.; Steegen, A.; Lindsay, R.; Sherony, M.; Narayanan, V.; Samavedam, S.; Theon, V.-Y.; Chudzik, M.; Schepis, D.; Haetty, J.; Chowdhury, M.; Kanarsky, T.; Yan, W.; Chen, J.; Zhuang, H.; Jaeger, D.; Chen, X.; Loesing, R.; Tang, T.; Hatzistergos, M.; Moumen, N.; von Arnim, K.; Han, S.; Schruefer, K.; Lee, Y.; Han, J.-P.; Li, W.; Yin, H.; Pacha, C.; Kim, N.; Ostermayr, M.; Eller, M.; Kim, S.; Kim, K.;
A voltage scaling model for performance evaluation in digital CMOS circuits
2009 / IEEE / 978-1-4244-5641-3
By: Schruefer, K.; von Arnim, K.; Berthold, J.; Pacha, C.; Schulz, T.; Hofmann, K.; Baumann, T.;

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