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Author: Zhijiong Luo

Results

High quality ultra-thin (1.5 nm) TiO/sub 2/-Si/sub 3/N/sub 4/ gate dielectric for deep sub-micron CMOS technology

1999 / IEEE / 0-7803-5410-9
By: Xiewen Wang; Xin Guo; Tamagawa, T.; Ma, T.P.; Zhijiong Luo;

Two silicon nitride technologies for post-SiO₂ MOSFET gate dielectric

2001 / IEEE
By: Dim-Lee Kwong; Xin Guo; Song, S.C.; Chenming Hu; Tsu-Jae King; Polishchuk, I.; Lin, R.; Yang, K.J.; Yee Chia Yeo; Qiang Lu; Tso-Ping Ma; Luan, H.F.; Xiewen Wang; Zhijiong Luo;

JVD silicon nitride as tunnel dielectric in p-channel flash memory

2002 / IEEE
By: Tso-Ping Ma; Jin-Ping Han; Zhijiong Luo; Wenjuan Zhu; Chenming Hu; Tsu-Jae King; Min She;

Low-voltage, fast-programming P-channel flash memory with JVD tunneling nitride

2001 / IEEE / 0-7803-7432-0
By: Zhijiong Luo; Wenjuan Zhu; Chenming Hu; Tsu-Jae King; Min She; Tso-Ping Ma; Jin-Ping Han;

Correlations of MOSFET transconductance: Its physical origins and relevance to analog MOSFET modeling and operation

2003 / IEEE
By: Zhijiong Luo; Stiles, K.; Shapira, S.;

A new method to extract EOT of ultrathin gate dielectric with high leakage current

2004 / IEEE
By: Ma, T.P.; Zhijiong Luo;

High performance cmos bulk technology using direct silicon bond (dsb) mixed crystal orientation substrates

2005 / IEEE / 0-7803-9268-X
By: Saenger, K.L.; Pfeiffer, G.; Ng, H.Y.; Haizhou Yin; Chun-Yung Sung; Wann, C.H.; Zhibin Ren; Rong Zhang; de Souza, J.P.; Sadana, D.; Rovedo, N.; Raccioppo, M.; Chan, V.; Nguyen, P.Y.; Mo, R.T.; Madan, A.; Zhijiong Luo; Lee, H.K.; Ku, V.; Kempisty, J.J.; Bendernagel, R.; Ott, J.A.; Jinghong Li; Crowder, S.W.;

Strained Si Channel MOSFETs with Embedded Silicon Carbon Formed by Solid Phase Epitaxy

2007 / IEEE / 978-4-900784-03-1
By: Chan, K.; Lavoie, C.; Dyer, T.; Byeong Kim; Chakravarti, A.; Ozcan, A.; Madan, A.; Jinghong Li; Gluschenkov, O.; Yaocheng Liu; Ken Rim; Henson, W.; Loesing, R.; Zhijiong Luo; Rovedo, N.; Pinto, T.; Popova, I.;

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